Google Reportedly Teams Up With AMD to Design Next-Generation TPU; CPU Core IP Is Key, Future of AI May Rely More on CPU-Intensive Computing

According to market reports cited in a SemiAnalysis client note, Google is collaborating with AMD to develop a product for its 10th-generation Tensor Processing Unit (TPU) line. This would mark AMD’s first major involvement in a custom AI Application-Specific Integrated Circuit (ASIC) project. Analysts note that Google has already built nine generations of TPUs, with Broadcom long handling the actual silicon design, meaning traditional TPU development does not require AMD’s involvement. Thus, the core draw of this partnership lies in AMD’s CPU intellectual property (IP), advanced packaging, and interconnect technologies. The report specifically points out that Google and its clients are pushing for integrating CPU cores within TPU packages to meet the demands of CPU-intensive workloads such as reinforcement learning. Traditional large language model (LLM) training still relies primarily on accelerators, but inference and reinforcement learning for agent-based models require more general-purpose compute resources to operate alongside accelerators. This trend is already evident in Google’s recent hardware deployments. The TPU 8i system, designed for inference and reinforcement learning workloads, pairs one Google Axion CPU with every two TPUs; by contrast, the 7th-generation TPU server only includes one Intel Xeon processor for every four TPUs. Sources say a 1:1 CPU-to-accelerator ratio is the optimal setup in certain scenarios, suggesting the future of AI computing may rely far more on CPUs than the market currently assumes. If the collaboration with AMD materializes, Google will combine its in-house TPU accelerators with AMD’s general-purpose compute cores to build a hybrid AI ASIC, which could reshape the competitive landscape of data center chips.