TSMC to raise wafer foundry prices by 3% to 6% starting next year, with order visibility extending to 2030.

TSMC has confirmed it will adjust wafer fabrication prices starting January 2027 based on process nodes, with an overall increase of 3% to 6%. Advanced processes such as 2nm and 3nm will see the highest hikes, while mature and specialty processes will be priced on a case-by-case basis depending on products, capacity utilization rates, and customer conditions. Currently, TSMC’s 8-inch wafer fabs are operating at over 100% capacity utilization, with processes below 45nm running at full capacity, and some order visibility extending as far as 2030. AI data center expansion is not only driving sustained demand for GPUs, ASICs, and HBM, but also boosting orders for mature-process chips including PMICs, MCUs, MOSFETs, and analog ICs. Supply chain sources note that 2nm and 3nm capacity remains tight, while capacity bottlenecks for advanced packaging like CoWoS have not been fully resolved, making it difficult for customers to avoid price hikes by switching suppliers in the short term. The price adjustment is also expected to ripple out to other foundries including Samsung Electronics, Intel, UMC, and Vanguard International Semiconductor (VIS), as well as sectors such as packaging and testing, and IC design. Industry insiders point out that growing demand for chips including power management units, network communication, and optical communication from AI servers has caused AI demand to spill over from advanced to mature processes, driving a rebound in capacity utilization for mature processes that previously faced weak supply-demand balances, and strengthening foundries’ bargaining power. Additionally, the heavy capital expenditure and cost pressures from TSMC’s overseas fab construction are also among the factors behind the price hike. Supply chain sources forecast that the 2027 wafer foundry price hikes may further push up costs across sectors including packaging and testing, substrates, materials, and memory.