TSMC’s A14 process reduces SRAM cell area to less than 0.017 square microns, restarting miniaturization efforts after an 8-year hiatus.

TSMC plans to shrink the area of high-density 6T SRAM (Static Random-Access Memory) bit cells to below 0.017 square micrometers in its A14 process, which is targeted for mass production in 2028. The move breaks a long-standing stagnation of around 0.021 square micrometers for SRAM cell size since the N5 process launched in 2020. According to reports, TSMC is expected to unveil the relevant research results by the end of the year. Based on currently disclosed data, the A14 process’s SRAM cell area is expected to outpace Intel’s 18A process; Intel previously announced its high-density SRAM cell size is 0.021 square micrometers. As Samsung has not yet disclosed the specific SRAM cell dimensions of its latest process, a direct comparison is currently not possible. SRAM is a critical storage component for on-chip caches in CPUs, GPUs, and AI accelerator chips. Shrinking the cell area allows more cache to be packed into the same chip area, helping alleviate data access bottlenecks in AI chips and improve performance and energy efficiency. TSMC noted that the A14 process targets a 10-15% performance gain, 25-30% power reduction, and roughly 20% higher chip density compared to its N2 process. The A14 process is currently progressing toward its 2028 mass production goal, but its final yield, cost, and customer adoption remain unconfirmed.