Chip experts: AI computing power bottlenecks are shifting from chips to packaging, interconnection, and storage.

Insight Beating AI News Flash: Veteran chip designer and hardware analyst Mr. Bubble stated in an interview on the Frictionless Podcast that the core bottleneck of AI computing infrastructure is shifting from simply boosting chip computing power to advanced packaging, system interconnection latency, and storage tier management. Mr. Bubble noted that the rapid rise in costs of advanced process nodes and the limited growth in transistor density have put traditional Moore’s Law under economic challenges. Instead of continuing to shrink process nodes, the industry is increasingly using advanced packaging to connect multiple chips into a single computing system. He pointed out that the basic unit of AI computing power in the future may no longer be a single chip or server, but a complete rack or even multiple racks, with PCB, packaging, and interconnection capabilities emerging as key limiting factors. On the storage front, he argued that as AI inference context windows expand, massive historical context data should not all occupy expensive High Bandwidth Memory (HBM). The industry may increasingly adopt flash memory offloading, keeping high-frequency data in HBM while migrating low-frequency context to larger-capacity, lower-cost storage layers. He further projected that 3D DRAM could become a key direction for next-generation memory technology. Regarding AI infrastructure investment, Mr. Bubble believes that as prefill and decoding gradually adopt a decoupled architecture, the importance of system-level hardware design will further rise. He also noted that compared to directly betting on large language model companies, enterprises with hardware, packaging, storage, and other key infrastructure capabilities may play a more long-term role in the AI industry chain.